1. Technical Field
The present invention relates to logic circuits in general, and in particular to flip-flop circuits. Still more particularly, the present invention relates to a multi-threshold flip-flop circuit having an outside feedback.
2. Description of the Prior Art
In order to maintain high performances in electronic devices having a scaled-down power supply voltage, threshold voltages for transistors within the electronic devices need to be scaled down also. However, a lower threshold voltage will give rise to a higher subthreshold leakage current. Especially for battery-powered electronic devices, the relative level of leakage currents increases even more during sleep mode. One solution for reducing the amount of current leakage in sleep mode is to use a circuit commonly known as multi-threshold complementary-metal-oxide semiconductor (MTCMOS) circuit. Generally speaking, a MTCMOS circuit uses low-threshold transistors during active mode but cuts off supply voltage during sleep mode. Such switching scheme works well for combinational circuits but not for sequential circuits because a latch or flip-flop circuit will lose its logical state when the supply voltage is turned off.
Several solutions have been utilized to tackle the problem of losing logical state in MTCMOS sequential circuits. Most of those solutions are generally based on duplicating the regular flip-flop circuit structure with some form of xe2x80x9cshadowxe2x80x9d or xe2x80x9cballoonxe2x80x9d latch. A duplicate latch can be built with high-threshold transistors that will keep the logical states of transistors during sleep mode. However, all the prior art solutions typically result in circuits having significant increased complexity with a large chip area overhead. In addition, most prior art solutions have non-trivial issues related to saving and restoring state. Consequently, it would be desirable to provide an improved flip-flop circuit with relatively low subthreshold leakage currents.
In accordance with a preferred embodiment of the present invention, a flip-flop circuit includes a master latch having a forward MTCMOS inverter and a feedback standard inverter, and a slave latch having a forward MTCMOS inverter and a feedback standard inverter. A first switch is connect to an input of the master latch. A second switch is connected between an output of the master latch and an input of the slave latch. A third switch is connected between an output of the slave latch and the input of the master latch.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.